Intel has very quietly pushed out their Ivy Bridge
graphics programming documentation and register specifications on
Friday. This Ivy Bridge graphics core programming documentation spans 17
files spread across three volumes and 2,468 pages of technical details
concerning their latest-generation graphics.
While Intel has a large team of developers within their Open-Source
Technology Center working on their open-source Linux graphics driver,
they continue to produce very detailed programming documentation for the
public. These documents cover the key registers for their hardware and
other information to benefit anyone wishing to get into low-level
graphics driver programming or just wanting to better understand how
Intel's latest graphics core works.
Intel is considered to be the best Linux friendly hardware vendor, contributing to open source at every chance they get.
Intel has put out documentation on their graphics chips for several
generations now and they just did so for Ivy Bridge. The Ivy Bridge
processors have been available since April, and the open-source Linux
code for the graphics driver has been available for more than a year, but they finally received permission to do the public drop of their programming documentation.
This Intel HD Graphics Open Source Programmer’s Reference Manual (PRM) describes the architectural behavior and programming environment of the Ivy Bridge chipset family. The Graphics Controller (GC) contains an extensive set of registers and instructions for configuration, 2D, 3D, and video systems. The PRM describes the register, instruction, and memory interfaces, and the device behaviors as controlled and observed through those interfaces. The PRM also describes the registers and instructions, and provides detailed bit/field descriptions.
This documentation appears to be rather complete from the initial look
through it this morning. There's just under 2,500 pages of information
spanning 17 PDF files. The graphics core is covered including the MMIO
registers, memory interface, render engine, blitter engine, and video
codec engine command streamer. There's also coverage on the GT interface
register, L3 cache and URB, 3D media pipeline, media and general
purpose pipeline, multi-format transcoder, VGA registers, PCI registers,
north/south display engines, message gateway, and execution unit ISA
Intel's documentation is available for unrestricted download here. Source: Phoronix
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